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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 2000 document no. m15085ej5v0ds00 (5th edition) date published october 2001 ns cp (k) printed in japan mos integrated circuit pd4616112 16m-bit cmos mobile specified ram 1m-word by 16-bit data sheet the mark shows major revised points. description the pd4616112 is a high speed, low power, 16,777,216 bits (1,048,576 words by 16 bits) cmos mobile specified ram featuring low power static ram compatible function and pin configuration. the pd4616112 is fabricated with advanced cmos technology using one-transistor memory cell. the pd4616112 is packed in 48-pin tape fbga. features ? 1,048,576 words by 16 bits organization ? fast access time: 80, 90 ns (max.) ? byte data control: /lb (i/o0 - i/o7), /ub (i/o8 - i/o15) ? low voltage operation: v cc = 2.6 to 3.0 v ? operating ambient temperature: t a = ?20 to +70 c ? output enable input for easy application ? chip enable input: /cs pin ? standby mode input: mode pin ? standby mode1: normal standby (memory cell data hold valid) ? standby mode2: memory cell data hold invalid product name access time operating supply operating ambient supply current ns (max.) voltage temperature at operating at standby c ma (max.) a (max.) pd4616112-bcxx 80, 90 2.6 to 3.0 ?20 to +70 35 100 / 10
data sheet m15085ej5v0ds 2 pd4616112 ordering information part number package access time operating operating remark ns (max.) supply voltage temperature vc pd4616112f9-bc80-bc2 48-pin tape fbga (8 x 6) 80 2.6 to 3.0 ?20 to +70 bc version pd4616112f9-bc90-bc2 90 marking image part number marking (xx) pd4616112f9-bc80-bc2 b1 pd4616112f9-bc90-bc2 b2 j ms16m0-xx index mark lot number
data sheet m15085ej5v0ds 3 pd4616112 pin configuration /xxx indicates active low signal. 48-pin tape fbga (8 x 6) a b c d e f g h 1 2 3 4 5 6 bottom view 6 5 4 3 2 1 top view remark refer to package drawing for the index mark. a0 - a19 : address inputs i/o0 - i/o15 : data inputs / outputs /cs : chip select mode : standby mode /we : write enable /oe : output enable /lb, /ub : byte data select v cc : power supply gnd : ground 123456 a/lb/oea0a1a2mode b i/o8 /ub a3 a4 /cs i/o0 c i/o9 i/o10 a5 a6 i/o1 i/o2 d gnd i/o11 a17 a7 i/o3 v cc ev cc i/o12 gnd a16 i/o4 gnd f i/o14 i/o13 a14 a15 i/o5 i/o6 g i/o15 a19 a12 a13 /we i/o7 h a18 a8 a9 a10 a11 gnd 654321 a mode a2 a1 a0 /oe /lb b i/o0 /cs a4 a3 /ub i/o8 c i/o2 i/o1 a6 a5 i/o10 i/o9 dv cc i/o3 a7 a17 i/o11 gnd e gnd i/o4 a16 gnd i/o12 v cc f i/o6 i/o5 a15 a14 i/o13 i/o14 g i/o7 /we a13 a12 a19 i/o15 h gnd a11 a10 a9 a8 a18
data sheet m15085ej5v0ds 4 pd4616112 block diagram address buffer memory cell array 16,777,216 bits input data controller a0 a19 i/o8 - i/o15 sense amplifier / switching circuit column decoder /we /oe /ub /lb output data controller i/o0 - i/o7 v cc gnd /cs mode address buffer refresh counter row decoder refresh control standby mode control
data sheet m15085ej5v0ds 5 pd4616112 truth table /cs mode /oe /we /lb /ub mode i/o supply current i/o0 - i/o7 i/o8 - i/o15 hh not selected (standby mode 1) high impedance high impedance i sb1 hl not selected (standby mode 2) high impedance high impedance i sb2 lhhh output disable high impedance high impedance i cca l h l l word read d out d out l h lower byte read d out high impedance h l upper byte read high impedance d out h h output disable high impedance high impedance lll word write d in d in l h lower byte write d in high impedance h l upper byte write high impedance d in h h write abort high impedance high impedance caution mode pin must be fixed to high except standby mode 2. remark : v ih or v il initialization the pd4616112 is initialized in the power-on sequence according to the following. (1) to stabilize internal circuits, before turning on the power, a 200 s or longer wait time must precede any signal toggling. (2) after the wait time, read operation must be performed at least 3 times. after that, it can be normal operation. initialization timing chart v cc v cc (min.) v ih (min.) v ih (min.) t rc t cp 200 s address (input) /cs (input) mode (input) wait time power on read operation 3 times normal operation cautions 1. following power application, make mode and /cs high level during the wait time interval. 2. following power application, make mode high level during the wait time and three read operations. 3. the read operation must satisfy the specs described on page 10 (read cycle (bc version)). 4. the address is don?t care (v ih or v il ) during read operation. 5. read operation must be executed with toggled the /cs pin. 6. to prevent bus contention, it is recommended to set /oe to high level. 7. do not input data to the i/o pins if /oe is low level during a read operation.
data sheet m15085ej5v0ds 6 pd4616112 electrical specifications absolute maximum ratings parameter symbol condition rating unit supply voltage v cc ? 0.5 note to +3.3 v input / output voltage v t ? 0.5 note to v cc + 0.4 (3.3 v max). v operating ambient temperature t a ? 20 to +70 c storage temperature t stg ? 55 to +125 c note ? 1.0 v (min.) (pulse width: 30 ns) caution exposing the device to stress above those listed in absolute maximum rating could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition pd4616112-bcxx unit min. max. supply voltage v cc 2.6 3.0 v high level input voltage v ih 0.8v cc v cc +0.3 v low level input voltage v il ? 0.3 note 0.2v cc v operating ambient temperature t a ? 20 +70 c note ? 0.5 v (min.) (pulse width: 30 ns) capacitance (t a = 25 c, f = 1 mhz) parameter symbol test condition min. typ. max. unit input capacitance c in v in = 0 v 8 pf input / output capacitance c i/o v i/o = 0 v 10 pf remarks 1. v in : input voltage v i/o : input / output voltage 2. these parameters are not 100% tested.
data sheet m15085ej5v0ds 7 pd4616112 dc characteristics (recommended operating conditions unless otherwise noted) parameter symbol test condition pd4616112-bcxx unit min. typ. max. input leakage current i li v in = 0 v to v cc ? 1.0 +1.0 a i/o leakage current i lo v i/o = 0 v to v cc , /cs = v ih or ? 1.0 +1.0 a /we = v il or /oe = v ih operating supply current i cca /cs = v il , minimum cycle time, 35 ma i i/o = 0 ma standby supply current i sb1 /cs v cc ? 0.2 v, mode v cc ? 0.2 v 100 a i sb2 /cs v cc ? 0.2 v, mode 0.2 v 10 high level output voltage v oh i oh = ? 0.5 ma 0.8v cc v low level output voltage v ol i ol = 1 ma 0.2v cc v remarks 1. v in : input voltage v i/o : input / output voltage 2. these dc characteristics are in common regardless of product classifications.
data sheet m15085ej5v0ds 8 pd4616112 standby mode state machine /cs = v ih , mode = v ih mode = v ih /cs = v ih , mode = v ih /cs = v ih , mode = v il /cs = v ih , mode = v il /cs = v il , mode = v ih /cs = v ih , mode = v ih /cs = v il power on wait 200 s dummy read operation (3 times) initial state active standby mode1 standby mode2 standby mode characteristics standby mode memory cell data hold standby supply current ( a) mode 1 valid 100 (i sb1 ) mode 2 invalid 10 (i sb2 )
data sheet m15085ej5v0ds 9 pd4616112 ac characteristics (recommended operating conditions unless otherwise noted) ac test conditions [ pd4616112-bc80, pd4616112-bc90 ] input waveform (rise and fall time 5 ns) test points 0.2 vcc 0.8 vcc vcc/2 vcc/2 vcc gnd 5ns output waveform test points vcc/2 vcc/2 output load ac characteristics directed with the note should be measured with the output load shown in figure 1 . figure 1 c l : 50 pf 5 pf (t clz , t olz , t blz , t chz , t ohz , t bhz , t whz , t ow ) i/o (output) 50 ? z o = 50 ? c l v cc /2
data sheet m15085ej5v0ds 10 pd4616112 read cycle (bc version) parameter symbol pd4616112-bc80 pd4616112-bc90 unit notes min. max. min. max. read cycle time t rc 80 10,000 90 10,000 ns 1 identical address read cycle time t rc1 80 10,000 90 10,000 ns 2 address skew time t skew 10 20 ns 3 /cs pulse width t cp 10 10 ns address access time t aa 80 90 ns 4 /cs access time t acs 80 90 ns /oe to output valid t oe 35 40 ns 5 /lb, /ub to output valid t ba 35 40 ns output hold from address change t oh 10 10 ns /cs to output in low impedance t clz 10 10 ns /oe to output in low impedance t olz 55ns /lb, /ub to output in low impedance t blz 55ns /cs to output in high impedance t chz 25 25 ns /oe to output in high impedance t ohz 25 25 ns /lb, /ub to output in high impedance t bhz 25 25 ns notes 1. one read cycle (t rc ) must satisfy the minimum value (t rc(min.) ) and maximum value (t rc(max.) = 10 s). t rc indicates the time from the /cs low level input point or address change start point, whichever is later, to the /cs high level input point or the next address change start point, whichever is earlier. as a result, there are the following four conditions for t rc . 1) time from address change start point to /cs high level input point (address access) 2) time from address change start point to next address change start point (address access) 3) time from /cs low level input point to next address change start point (/cs access) 4) time from /cs low level input point to /cs high level input point (/cs access) 2. the identical address read cycle time (t rc1 ) is the cycle time of one read operation when performing continuous read operations toggling /oe , /lb, and /ub with the address fixed and /cs low level. perform settings so that the sum (t rc ) of the identical address read cycle times (t rc1 ) is 10 s or less. 3. t skew indicates the following three types of time depending on the condition. 1) when switching /cs from high level to low level, t skew is the time from the /cs low level input point until the next address is determined. 2) when switching /cs from low level to high level, t skew is the time from the address change start point to the /cs high level input point. 3) when /cs is fixed to low level, t skew is the time from the address change start point until the next address is determined. since specs are defined for t skew only when /cs is active, t skew is not subject to limitations when /cs is switched from high level to low level following address determination, or when the address is changed after /cs is switched from low level to high level. 4. regarding t aa and t acs , only t aa is satisfied during address access (refer to 1) and 2) of note 1 ), and only t acs is satisfied during /cs access (refer to 3) of note 1 ). 5. regarding t ba and t oe , only t ba is satisfied if /oe becomes active later than /ub and /lb, and only t oe is satisfied if /ub and /lb become active before /oe.
data sheet m15085ej5v0ds 11 pd4616112 read cycle timing chart 1 t chz t oh t clz t acs /cs (input) i/o (output) t blz t ba t bhz /oe (input) /lb, /ub (input) t oe t skew t skew t cp t cp t rc t olz t ohz t chz t clz t acs i/o (output) t blz t ba t bhz /oe (input) /lb, /ub (input) t oe t skew t cp t cp t rc t olz t ohz /cs (input) t skew high impedance high impedance address (input) address (input) data out data out caution if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the read cycle time (t rc ), none of the data can be guaranteed. remark in read cycle, /we should be fixed to high.
data sheet m15085ej5v0ds 12 pd4616112 t acs /cs (input) address (input) i/o (output) /oe (input) t skew t skew t skew /lb, /ub (input) data out data out data out data out data out high impedance t rc t rc t aa t oe t olz t blz t oh t cp t rc t chz t acs t clz t bhz t ba t blz t skew t cp t rc t chz t acs t clz t bhz t ba t blz t bhz t chz t oh t aa t ohz t rc t clz t ba t oh caution if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the read cycle time (t rc ), none of the data can be guaranteed. remark in read cycle, /we should be fixed to high. read cycle timing chart 2
data sheet m15085ej5v0ds 13 pd4616112 t acs /cs (input) address (input) i/o8~15 (output) /oe (input) t skew /lb (input) t clz t skew t skew t skew t skew t rc t rc t rc t rc t rc i/o0~7 (output) /ub (input) data out data out data out data out hi-z high impedance t blz t blz t olz t oe t ba t ba t oh t bhz t bhz t ohz t oh t oh t bhz t ohz t oh t bhz t ohz t aa t blz t olz t oe t ba t blz t olz t oe t ba t aa caution if the address is changed using a value that is either lower than the minimum value or higher than the maximum value f or the read cycle time (t rc ), none of the data can be guaranteed. remark in read cycle, /we should be fixed to high. read cycle timing chart 3
data sheet m15085ej5v0ds 14 pd4616112 read cycle timing chart 4 /cs (input) address (input) /lb, /ub (input) data out i/o (output) t skew t skew high impedance high impedance t rc1 t ba t ba t rc1 t rc /oe (input) t acs t oe t oe data out t olz t blz t olz t blz t ohz t bhz t ohz t bhz note note caution if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the read cycle time (t rc ), none of the data can be guaranteed. note to perform a continuous read toggling /oe, /ub, and /lb with /cs low level at an identical address, make settings so that the sum (t rc ) of the identical address read cycle times (t rc1 ) is 10 s or less. remark in read cycle, /we should be fixed to high.
data sheet m15085ej5v0ds 15 pd4616112 write cycle (bc version) parameter symbol pd4616112-bc80 pd4616112-bc90 unit notes min. max. min. max. write cycle time t wc 80 10,000 90 10,000 ns 1 identical address write cycle time t wc1 80 10,000 90 10,000 ns 2 address skew time t skew 10 20 ns 3 /cs to end of write t cw 40 50 ns 4 /lb, /ub to end of write t bw 30 35 ns address valid to end of write t aw 35 45 ns write pulse width t wp 30 35 ns write recovery time t wr 20 20 ns 5 /cs pulse width t cp 10 10 ns address setup time t as 00ns byte write hold time t bwh 20 20 ns data valid to end of write t dw 20 25 ns data hold time t dh 00ns /oe to output in low impedance t olz 55ns /we to output in high impedance t whz 25 25 ns /oe to output in high impedance t ohz 25 25 ns output active from end of write t ow 55ns notes 1. one write cycle (t wc ) must satisfy the minimum value (t wc(min.) ) and the maximum value (t wc(max.) = 10 s). t wc indicates the time from the /cs low level input point or address change start point, whichever is after, to the /cs high level input point or the next address change start point, whichever is earlier. as a result, there are the following four conditions for t wc . 1) time from address change start point to /cs high level input point 2) time from address change start point to next address change start point 3) time from /cs low level input point to next address change start point 4) time from /cs low level input point to /cs high level input point 2. the identical address read cycle time (t wc1 ) is the cycle time of one write cycle when performing continuous write operations with the address fixed and /cs low level, changing /lb and /ub at the same time, and toggling /we, as well as when performing a continuous write toggling /lb and /ub. make settings so that the sum (t wc ) of the identical address write cycle times (t wc1 ) is 10 s or less. 3. t skew indicates the following three types of time depending on the condition. 1) when switching /cs from high level to low level, t skew is the time from the /cs low level input point until the next address is determined. 2) when switching /cs from low level to high level, t skew is the time from the address change start point to the /cs high level input point. 3) when /cs is fixed to low level, t skew is the time from the address change start point until the next address is determined. since specs are defined for t skew only when /cs is active, t skew is not subject to limitations when /cs is switched from high level to low level following address determination, or when the address is changed after /cs is switched from low level to high level.
data sheet m15085ej5v0ds 16 pd4616112 4. definition of write start and write end /cs /we /lb, /ub status write start pattern 1 h to l l l if /we, /lb, /ub are low level, time when /cs changes from high level to low level write start pattern 2 l h to l l if /cs, /lb, /ub are low level, time when /we changes from high level to low level write start pattern 3 l l h to l if /cs, /we are low level, time when /lb or /ub changes from high level to low level write end pattern 1 l l to h l if /cs, /we, /lb, /ub are low level, time when /we changes from low level to high level write end pattern 2 l l l to h when /cs, /we, /lb, /ub are low level, time when /lb or /ub changes from low level to high level 5. definition of write end recovery time (t wr ) 1) time from write end to address change start point, or from write end to /cs high level input point 2) when /cs, /lb, /ub are low level and continuously written to the identical address, time from /we high level input point to /we low level input point 3) when /cs, /we are low level and continuously written to the identical address, time from /lb or /ub high level input point, whichever is later, to /lb or /ub low level input point, whichever is earlier. 4) when /cs is low level and continuously written to the identical address, time from write end to point at which /we , /lb, or /ub starts to change from high level to low level, whichever is earliest.
data sheet m15085ej5v0ds 17 pd4616112 write cycle timing chart 1 t bw t dw t dh high impedance address (input) /lb, /ub (input) i/o (input) /cs (input) t wp t wr /we (input) t skew t cp high impedance t wc t cw t skew t dw t dh t as t wp t wr t as t bw t wc t cw t bw t dw t dh high impedance address (input) /lb, /ub (input) i/o (input) /cs (input) t wp t wr /we (input) t skew t cp high impedance t wc t skew t dw t dh t wp t wr t bw t wc t cw t cw t skew data in data in data in data in cautions 1. during address transition, at least one of pins /cs, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (t wc ), none of the data can be guaranteed. remark write operation is done during the overlap time of a low /cs, /we, /lb and/or /ub.
data sheet m15085ej5v0ds 18 pd4616112 write cycle timing chart 2 (/we controlled) t cw t aw /cs (input) address (input) t as t wp /we (input) t skew t skew t aw t dw t dh i/o (input / output) t wr t ow t aw t skew t cp t whz high impedance high impedance high impedance /oe (input) t ohz t olz t wp t as t as t wc t wc t wc t wp t wr t wr t dw t dh t dw t dh t skew /cs (input) address (input) /we (input) t dw t dh i/o (input) t skew t skew high impedance high impedance high impedance t wc1 t as t wp t wp t wr t dw t dh t wc1 /lb, /ub (input) t bw t skew t wc t wr data in data in data in data in data in high impedance high impedance indefinite data out note note cautions 1. during address transition, at least one of pins /cs, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (t wc ), none of the data can be guaranteed. note if /lb and /ub are changed at the same time with /cs low level and a continuous write operation toggling /we is performed, make settings so that the sum (t wc ) of the identical address write cycle time (t wc1 ) is 10 s or less. remarks 1. write operation is done during the overlap time of a low /cs, /we, /lb and/or /ub. 2. when /we is at low, the i/o pins are always high impedance. when /we is at high, read operation is executed. therefore /oe should be at high to make the i/o pins high impedance.
data sheet m15085ej5v0ds 19 pd4616112 write cycle timing chart 3 (/cs controlled) t as t cw i/o (input) t wr t wc /we (input) /cs (input) address (input) /lb, /ub (input) t dw t dh high impedance high impedance high impedance t wc t dw t dh t cw t wr t as t as t cw i/o (input) t wr t wc /we (input) /cs (input) address (input) /lb, /ub (input) t dw t dh high impedance high impedance high impedance t wc t dw t dh t cw t wr t as data in data in data in data in cautions 1. during address transition, at least one of pins /cs, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (t wc ), none of the data can be guaranteed. remark write operation is done during the overlap time of a low /cs, /we, /lb and/or /ub.
data sheet m15085ej5v0ds 20 pd4616112 write cycle timing chart 4 (/lb, /ub controlled 1) t bw t dw t dh high impedance address (input) /lb, /ub (input) i/o (input) /cs (input) t wp /we (input) t skew high impedance t wc t cw t skew t dw t dh t wr t as t bw t as t wc t aw t wr t bw t dw t dh high impedance address (input) /lb, /ub (input) i/o (input) /cs (input) t wp t wr /we (input) t skew high impedance t wc t cw t skew t dw t dh t as t wc t bw t as t wr t aw data in data in data in data in cautions 1. during address transition, at least one of pins /cs, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (t wc ), none of the data can be guaranteed. remark write operation is done during the overlap time of a low /cs, /we, /lb and/or /ub.
data sheet m15085ej5v0ds 21 pd4616112 write cycle timing chart 5 (/lb, /ub controlled 2) /cs (input) address (input) /lb, /ub (input) t dw t dh i/o (input) t skew t skew high impedance high impedance high impedance t wc1 t as t bw t bw t wr t dw t dh t wc1 t wr t wc /we (input) t wp data in data in note note cautions 1. during address transition, at least one of pins /cs, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (t wc ), none of the data can be guaranteed. note if /lb and /ub are changed at the same time with /cs low level and a continuous write operation toggling /we is performed, make settings so that the sum (t wc ) of the identical address write cycle time (t wc1 ) is 10 s or less. remark write operation is done during the overlap time of a low /cs, /we, /lb and/or /ub.
data sheet m15085ej5v0ds 22 pd4616112 write cycle timing chart 6 (/lb, /ub independent controlled 1) t wp t as t cw i/o0 - 7 (input) t wr t wc1 /we (input) /cs (input) address (input) /lb (input) t bw high impedance high impedance /ub (input) t bw t wc1 t dw t dh t wr i/o8 - 15 (input) high impedance high impedance t dw t dh t wc data in data in note note cautions 1. during address transition, at least one of pins /cs, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (t wc ), none of the data can be guaranteed. note if /lb and /ub are changed at the same time with /cs low level and a continuous write operation toggling /we is performed, make settings so that the sum (t wc ) of the identical address write cycle time (t wc1 ) is 10 s or less. remark write operation is done during the overlap time of a low /cs, /we, /lb and/or /ub.
data sheet m15085ej5v0ds 23 pd4616112 write cycle timing chart 7 (/lb, /ub independent controlled 2) t wp t as t cw i/o0 - 7 (input) t wc /we (input) /cs (input) address (input) /lb (input) t bw high impedance high impedance /ub (input) t bw t dw t dh i/o8 - 15 (input) high impedance high impedance t dw t dh t wr t wr t as t bwh t cw t wp data in data in cautions 1. during address transition, at least one of pins /cs, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (t wc ), none of the data can be guaranteed. remark write operation is done during the overlap time of a low /cs, /we, /lb and/or /ub.
data sheet m15085ej5v0ds 24 pd4616112 read write cycle (bc version) parameter symbol min. max. unit notes read write cycle time t rwc 10,000 ns 1, 2 byte write setup time t bws 20 ns byte read setup time t brs 20 ns notes 1. make settings so that the sum (t rwc ) of the identical address read cycle time (t rc1 ) and the identical address write cycle time (t wc1 ) is 10 s or less when a write is performed at the identical address using /ub following a read using /lb with /cs low level, or when a write is performed using /lb following a read using /ub. 2. make settings so that the sum (t rwc ) of the identical address read cycle time (t rc1 ) and the identical address write cycle time (t wc1 ) is 10 s or less when a read is performed at the identical address using /ub following a write using /lb with /cs low level, or when a read is performed using /lb following a write using /ub.
data sheet m15085ej5v0ds 25 pd4616112 read write cycle timing chart 1 (/lb, /ub independent controlled 1) t wp i/o0 - 7 (output) t bws t rc1 /we (input) /cs (input) address (input) /lb (input) high impedance high impedance /ub (input) t bw t wc1 t wr i/o8 - 15 (input) high impedance high impedance t dw t dh t rwc t clz t blz t bhz t acs t aa data in data out note note cautions 1. during address transition, at least one of pins /cs, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the identical address read cycle time (t rc1 ) and the identical address write cycle time (t wc1 ), none of the data can be guaranteed. note make settings so that the sum (t rwc ) of the identical address read cycle time (t rc1 ) and the identical address write cycle time (t wc1 ) is 10 s or less when a write is performed at the identical address using /ub following a read using /lb with /cs low level, or when a write is performed using /lb following a read using /ub. remark write operation is done during the overlap time of a low /cs, /we, /lb and/or /ub.
data sheet m15085ej5v0ds 26 pd4616112 read write cycle timing chart 2 (/lb, /ub independent controlled 2) t wp i/o0 - 7 (input) t rc1 /we (input) /cs (input) address (input) /lb (input) high impedance high impedance /ub (input) t bw t wc1 t wr i/o8 - 15 (output) high impedance high impedance t dw t dh t rwc t blz t bhz t brs t ba t cw t as data in data out note note cautions 1. during address transition, at least one of pins /cs, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the identical address read cycle time (t rc1 ) and the identical address write cycle time (t wc1 ), none of the data can be guaranteed. note make settings so that the sum (t rwc ) of the identical address read cycle time (t rc1 ) and the identical address write cycle time (t wc1 ) is 10 s or less when a write is performed at the identical address using /ub following a read using /lb with /cs low level, or when a write is performed using /lb following a read using /ub. remark write operation is done during the overlap time of a low /cs, /we, /lb and/or /ub.
data sheet m15085ej5v0ds 27 pd4616112 read write cycle timing chart 3 (/lb, /ub independent controlled 3) t bw i/o0 - 7 (input) t rc1 /we (input) /cs (input) address (input) /lb (input) high impedance high impedance /ub (input) t wp t wc1 t wr i/o8 - 15 (output) high impedance high impedance t dw t dh t rwc t blz t bhz t ba t cw t as data in data out note note cautions 1. during address transition, at least one of pins /cs, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the identical address read cycle time (t rc1 ) and the identical address write cycle time (t wc1 ), none of the data can be guaranteed. note make settings so that the sum (t rwc ) of the identical address read cycle time (t rc1 ) and the identical address write cycle time (t wc1 ) is 10 s or less when a write is performed at the identical address using /ub following a read using /lb with /cs low level, or when a write is performed using /lb following a read using /ub. remark write operation is done during the overlap time of a low /cs, /we, /lb and/or /ub.
data sheet m15085ej5v0ds 28 pd4616112 standby mode 2 entry and recovery timing chart address (input) /cs (input) mode (input) t cm t rc t cp 200 s wait time read operation 3 times normal operation standby mode 2 (data invalid) parameter symbol min. max. unit note /cs high to mode low t cm 0ns cautions 1. make mode and /cs high level during the wait time. 2. make mode high level during the wait time and three read operations. 3. the read operation must satisfy the specs described on page 10 (read cycle (bc version)). 4. the read operation address can be either v ih or v il . 5. perform reading by toggling /cs. 6. to prevent bus contention, it is recommended to set /oe to high level. 7. do not input data to the i/o pins if /oe is low level during a read operation.
data sheet m15085ej5v0ds 29 pd4616112 package drawing s wb s wa 6 5 4 3 2 1 a b a b c d e f g h s y s y1 m s b x ab s 48-pin tape fbga (8x6) item millimeters d e 8.0 0.1 6.0 0.1 w a 0.2 0.94 0.10 b x 0.08 y 0.1 e 0.75 a1 0.24 0.05 a2 0.70 0.40 0.05 index mark index mark a a2 a1 ze zd y1 0.2 zd 1.125 ze 1.375 p48f9-75-bc2 e e d
data sheet m15085ej5v0ds 30 pd4616112 recommended soldering conditions please consult with our sales offices for soldering conditions of the pd4616112. type of surface mount device pd4616112f9-bcxx-bc2: 48-pin tape fbga (8 x 6)
data sheet m15085ej5v0ds 31 pd4616112 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd4616112 m8e 00. 4 the information in this document is current as of october, 2001. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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